Advantech MIC-5332 Bedienungsanleitung PDF herunterladen (Seite 45)

4.1 Overview

A complete management mechanism is strength of AdvancedTCA. An on board IPMC

(Intelligent Platform Management Controller) is in charge of collecting board

information (e.g. sensor events, health status, hot swap, etc.), log events to a

repository, and forwards them to the ShMC (Shelf Manager Controller). The shelf

manager will take actions based on these messages as needed.

4.2 Intelligent Platform Management Controller

A NXP LPC1768 microprocessor and a Lattice LatticeXP2 FPGA form the

management block of the MIC-5332. The system management solution is based on

Advantech IPMI Core G02 which is Advantech’s ATCA System Management

implementation. Its core is a NXP LPC1768 Cortex-M based CPU running on an

RTOS. For the list of supported IPMI commands by Advantech, please refer to

Appendix A, IPMI/PICMG Command Subset Supported by IPMC

A Lattice LFXP2F17 FPGA is used to provide additional connectivity for the IPMC and

payload. It provides extension interfaces with configurable routing options as well as

some additional stand-alone functionality.

One of the very basic benefits of Advantech IPMI Core G02 is the high level of

flexibility. Its modular structure allows the same firmware core to be used on different

xTCA platforms, sharing a high percentage of identical code.

4.2.1 IPMC Interface

In this section, we will describe the four different IPMC communication interfaces

(listed as below) of the MIC-5332.

 IPMC ←→ ShMC: IPMB-0

 IPMC ←→ RTM: IPMB-L

 IPMC ←→ payload: KCS

 IPMC ←→ Ethernet through NC-SI on BI/IO

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Advantech MIC-5332 Bedienungsanleitung Seite 45