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Advantech SOM-Express Design Guide
Chapter 3 Pin Assignments 35
3.4 Row D
Table 3.5 Connector D Pin Assignments
Pin Signal I/F I/O P Pin Signal I/F I/O P
D1 GND (FIXED) PWR PWR* - D56 PEG_TX1- PCIE O
D2 IDE_D5 IDE IO VCC3/5 D57 TYPE2# MISC PDS -
D3 IDE_D10 IDE IO VCC3/5 D58 PEG_TX2+ PCIE O AC on
D4 IDE_D11 IDE IO VCC3/5 D59 PEG_TX2- PCIE O AC on
D5 IDE_D12 IDE IO VCC3/5 D60 GND (FIXED) PWR PWR* -
D6 IDE_D4 IDE IO VCC3/5 D61 PEG_TX3+ PCIE O AC on
D7 IDE_D0 IDE IO VCC3/5 D62 PEG_TX3- PCIE O AC on
D8 IDE_REQ IDE I VCC3/5 D63 RSVD RSVD - -
D9 IDE_IOW# IDE O VCC3 D64 RSVD RSVD - -
D10 IDE_ACK# IDE O VCC3 D65 PEG_TX4+ PCIE O AC on
D11 GND (FIXED) PWR PWR* - D66 PEG_TX4- PCIE O AC on
D12 IDE_IRQ IDE I VCC3/5 D67 GND PWR PWR* -
D13
IDE_A0
IDE O VCC3 D68 PEG_TX5+ PCIE O
AC on
D14
IDE_A1
IDE O VCC3 D69 PEG_TX5- PCIE O
AC on
D15 IDE_A2 IDE O VCC3 D70 GND(FIXED) PWR PWR* -
D16
IDE_CS1#
IDE O VCC3 D71 PEG_TX6+ PCIE O
AC on
D17
IDE_CS3#
IDE O VCC3 D72 PEG_TX6- PCIE O
AC on
D18 IDE_RESET# IDE O VCC3 D73 SDVO_CLK SDVO O VCC2.5
D19
PCI_GNT3#
PCI
O
VCC3/5
D74
PEG_TX7+ PCIE
O
AC on
D20
PCI_REQ3#
PCI
I
VCC3/5
D75
PEG_TX7- PCIE
O
AC on
D21 GND (FIXED) PWR PWR* - D76 GND PWR PWR* -
D22 PCI_AD1 PCI IO VCC3/5 D77 IDE_CBLID# IDE I VCC3/5
D23
PCI_AD3
PCI IO VCC3/5 D78
PEG_TX8+ PCIE
O
AC on
D24
PCI_AD5
PCI IO VCC3/5 D79 PEG_TX8- PCIE O
AC on
D25 PCI_AD7 PCI IO VCC3/5 D80 GND(FIXED) PWR PWR* -
D26
PCI_C/BE0#
PCI IO VCC3/5 D81 PEG_TX9+ PCIE O
AC on
D27
PCI_AD9
PCI IO VCC3/5 D82 PEG_TX9- PCIE O
AC on
D28 PCI_AD11 PCI IO VCC3/5 D83 RSVD RSVD - -
D29 PCI_AD13 PCI IO VCC3/5 D84 GND PWR PWR* -
D30
PCI_AD15
PCI IO VCC3/5 D85
PEG_TX10+
PCIE O
AC on
D31
GND (FIXED)
PWR
PWR*
- D86
PEG_TX10-
PCIE
O
AC on
D32
PCI_PAR
PCI
IO
VCC3/5
D87
GND
PWR PWR* -
D33
PCI_SERR#
PCI
IO OD
VCC3/5
D88
PEG_TX11+
PCIE O
AC on
D34
PCI_STOP#
PCI
IO
VCC3/5
D89
PEG_TX11-
PCIE O
AC on
D35
PCI_TRDY#
PCI
IO
VCC3/5
D90
GND (FIXED)
PWR PWR* -
D36
PCI_FRAME#
PCI
IO
VCC3/5
D91
PEG_TX12+
PCIE O
AC on
D37
PCI_AD16
PCI IO VCC3/5 D92
PEG_TX12-
PCIE O
AC on
D38 PCI_AD18 PCI IO VCC3/5 D93 GND PWR PWR* -
D39
PCI_AD20
PCI IO VCC3/5 D94
PEG_TX13+
PCIE O
AC on
D40
PCI_AD22
PCI IO VCC3/5 D95
PEG_TX13-
PCIE O
AC on
D41 GND (FIXED) PWR PWR* - D96 GND PWR PWR* -
D42 PCI_AD24 PCI IO VCC3/5 D97 PEG_ENABL# PCIE I VCC3
D43
PCI_AD26
PCI IO VCC3/5 D98
PEG_TX14+
PCIE O
AC on
D44
PCI_AD28
PCI IO VCC3/5 D99
PEG_TX14-
PCIE O
AC on
D45 PCI_AD30 PCI IO VCC3/5 D100 GND (FIXED) PWR PWR* -
D46
PCI_IRQC#
PCI
I
VCC3/5
D101
PEG_TX15+
PCIE O
AC on
D47
PCI_IRQD#
PCI
I
VCC3/5
D102
PEG_TX15-
PCIE O
AC on
D48
PCI_CLKRUN#
PCI
IO
VCC3/5
D103
GND
PWR PWR* -
D49
PCI_M66EN
PCI
I
VCC3/5
D104
VCC_12V
PWR PWR* -
D50
PCI_CLK
PCI
O
VCC3/5
D105
VCC_12V
PWR PWR* -
D51 GND(FIXED) PWR PWR* - D106 VCC_12V PWR PWR* -
D52 PEG_TX0+ PCIE O AC on D107 VCC_12V PWR PWR* -
D53 PEG_TX0- PCIE O AC on D108 VCC_12V PWR PWR* -
D54 PEG_LANE_RV# PCIE I VCC3 D109 VCC_12V PWR PWR* -
D55 PEG_TX1+ PCIE O AC on D110 GND (FIXED) PWR PWR* -
- Advantech 1
- Notices 2
- Revision History 2
- Table of Contents 3
- 4 Table of Contents 4
- Table of Contents 5 5
- 6 Table of Contents 6
- Table of Contents 7 7
- 8 Table of Contents 8
- Chapter 1 Introduction 9
- 1.2 Referenced Documents 10
- 2.1 Overview 11
- 2.2 Specifications 13
- 2.2.1 SOM-5780 14
- 2.2.2 SOM-5782 16
- 2.2.3 SOM-DB5700 18
- 2.3 System Resources 19
- 2.3.1 SOM-5780 Resources 19
- 2.3.2 SOM-5782 Resources 22
- 2.4 PCI Routing 25
- 2.5 DC Specifications 25
- 2.5.1 Interface I/O Voltage 25
- 2.5.1.3 Audio 27
- 2.5.1.4 VGA 27
- 2.5.1.5 LCD 28
- 2.5.1.6 IDE 28
- 2.5.1.7 Ethernet 28
- 2.5.1.8 TV-Out Bus 28
- 2.5.1.9 IrDA 28
- 2.6 AC Specification 29
- 2.6.1 PCI-Bus AC Spec 29
- 2.6.3 Audio AC Spec 29
- 2.6.4 VGA AC Spec 29
- 2.6.5 IDE AC Spec 30
- 2.6.6 I2C AC Spec 30
- 2.6.7 SMBus AC Spec 30
- Chapter 3 Pin Assignments 31
- 3.1 Row A 32
- 3.2 Row B 33
- 3.3 Row C 34
- 3.4 Row D 35
- 4.1 Nominal Board Stack-Up 36
- Thickness 37
- 4.3 Alternate Stack Ups 39
- 5.1 PCI-Bus 40
- 5.1.1 Signal Description 40
- 5.1.2 Design Guidelines 41
- Vtest 0.4 Vcc 1.5 V 42
- Tskew 2 (max) 2 (max) ns 42
- 5.1.3 Layout Guidelines 44
- Carrier 45
- 5.1.4 Application Notes 46
- 5.2.1 Signal Description 47
- 5.2.2 Design Guidelines 47
- 5.2.3 Layout Guideline 48
- SOM-Express 49
- USB Connector 49
- 5.2.3.4 Stubs 50
- 5.3.1 Signal Description 51
- 5.3.2 Design Guidelines 51
- 5.3.2.3 Azalia: 52
- Analog Ground 53
- 5.3.3 Layout Guidelines 54
- ± 15% 54
- 5.4 VGA 56
- 5.4.1 Signal Description 56
- 5.4.2 Design Guidelines 57
- 5.4.3 Layout Guideline 57
- VGA Connector 58
- 5.5 LVDS 59
- 5.5.1 Signal Description 59
- 5.5.2 Design Guideline 59
- 5.5.3 Layout Requirements 60
- 5.6 Primary IDE0 61
- 5.6.1 Signal Description 61
- 5.6.2 Design Guidelines 61
- IDE bus IDE cable 62
- Total Max 62
- Length 13 inches 62
- Carrier Board 62
- 5.6.3 Layout Guidelines 63
- 5.7 Ethernet 64
- 5.7.1 Signal Descriptions 64
- 5.7.2 Design Guidelines 64
- LAN Connector 65
- 5.7.3 Layout Guidelines 66
- 5.7.3.2 Transformer 67
- 5.7.3.3 Critical Dimensions 68
- 5.8 TV-Out 70
- 5.8.1 Signal Descriptions 70
- 5.8.2 Design Guidelines 70
- TV DAC Filter 71
- 5.9 Miscellaneous 72
- Carrier board 74
- 5.10 PCI Express Bus 77
- 5.10.1 Signal Description 77
- Pin Signal I/O Description 77
- 5.10.3.1 Differential pairs 81
- Guidelines 82
- L1 L2 L3 Capacitor Value 83
- L1 L2 Capacitor Value 83
- 5.11 Serial ATA 84
- 5.11.1 Signal Description 84
- 5.11.2 Design Guidelines 84
- 5.11.3 Layout Guidelines 85
- 5.12 LPC 87
- 5.12.1 Signal Description 87
- 5.12.2 Design Guidelines 87
- 5.12.3 Layout Guidelines 87
- 5.12.4 Application Notes 88
- 5.12.4.3 LPT/Floppy 89
- 5.12.4.4 EMI Considerations 89
- Parallel Port 90
- 6.2 Design Guidelines 95
- 8.1 Material of Heatsink 101
- 8.4 Grounding Issues 102
- 8.8.1 Vendor List 106
- 8.8.2 Heat-Spreader 106
- 8.8.3 Heat-Sink 107
- 8.8.4 Thermal Pad 108
- M2.5*6 5 109
- M2.5*16 5 109
- Quantity 109
- 8.8.6 Fan 110
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