Advantech PCM-9388 Bedienungsanleitung PDF herunterladen (Seite 31)

23 PCM-9388 User Manual

Chapter 3 BIOS Operation

3.2.4 Advanced Chipset Features

 DRAM Timing Selectable [By SPD]

This item enables users to set the optimal timings for items 2 through 5, system

default setting of “By SPD” to follow the SPD information and ensure the system

running in stable and optimal performance.

 CAS Latency Time [Auto]

This item enables users to set the timing delay in clock cycles before SDRAM

starts a read command after receiving it.

 Active to Precharge Delay [7]

This item enables users to control the memory back’s minimum row active time

(tRAS); system default setting is “7”.

 DRAM RAS# to CAS# Delay [3]

This item enables users to set the timing of the transition from RAS (row

address strobe) to CAS (column address strobe) as both rows and column are

separately addressed shortly after DRAM is refreshed.

 DRAM RAS# Precharge [3]

This item enables users to set the DRAM RAS# precharge timing, system

default setting is “3”.

 DRAM Data Integrity Mode [Non-ECC]

This item enables users to set the DRAM Type of Error data correction, system

default setting is “Non-ECC”.

 MGM Core Frequency [Auto Max 266MHz]

This item enables users to set the operation speed of internal Graphic Chip FSB

and DRAM, system default setting is “Auto Max 266 MHz”.

 System BIOS Cacheable [Enabled]

This item allows the system BIOS to be cached to allow faster execution and

better performance.

 Video BIOS Cacheable [Disabled]

Note! The "Advanced Chipset Features" option controls the configuration of

the board's chipset and is chipset independent, for controlling chipset

ommended only technical users make changes to the default settings.

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Advantech PCM-9388 Bedienungsanleitung Seite 31