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29 PCI-1761 User Manual

Appendix C Register Structure and Format

C.7 I n t e r r u p t C o n t r o l R e g i s t e r - B A S E + 3 H / 4 H / 5 H

The Interrupt Control Register control the status of two interrupt signal sources (IDI0

~ IDI7). The user can clear the interrupt by writing its corresponding value to the

Interrupt Control Register, as shown in below table.

IDInCLR Interrupt clear control bits (n = 0 ~ 7)

This bit must first be cleared to service the next interrupt.

0 Don't care

1 Clear the interrupt

IDInRF Interrupt enable control bits (n = 0 ~ 7)

Read this bit to Enable/Disable the interrupt.

0 Disable

1 Enable

IDInEN Interrupt triggering control bits (n = 0 ~ 7)

The interrupt can be triggered by a rising edge or

falling edge of the interrupt signal, as determined by

the value in this bit.

0 Rising edge trigger

1 Falling edge trigger

Appendix



Table C.6: Register for Interrupt Control

Write Interrupt Control Register

Bit # 76543210

BASE +3H IDI7EN IDI6EN IDI5EN IDI4EN IDI3EN IDI2EN IDI1EN IDI0EN

BASE +4H IDI7RF IDI6RF IDI5RF IDI4RF IDI3RF IDI2RF IDI1RF IDI0RF

BASE +5H IDI7CLR IDI6CLR IDI5CLR IDI4CLR IDI3CLR IDI2CLR IDI1CLR IDI0CLR

1 2 ... 30 31 32 33 34 35 36

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